Micro Computer Control Corp. MA51 (T) 8051 Relocatable Macro Assembler Version 1.14 07-JAN-93 PUTCHAR Sat Jan 08 19:40:42 2005 PAGE 1 OBJECT MODULE PLACED IN PUTCHAR.OBJ ASSEMBLER INVOKED BY: MA51 PUTCHAR.SRC LOC OBJ LINE SOURCE 2 ;This code is listed here for entertainment value only, it should 3 ;not be used for anything important. Do not use this for a saleable product. 4 ;Feel free to pass this on to others in it's entirety. along with this message. 5 ;No Guarantees implicit or otherwise are implied, your mileage may vary. 8 9 $RB(0) 10 $RB(1) =1 11 $NOMOD51 INCLUDE(87C752.pdf) =1 13 ;This code is listed here for entertainment value only, it should =1 14 ;not be used for anything important. Do not use this for a saleable product. =1 15 ;Feel free to pass this on to others in it's entirety. along with this message. =1 16 ;No Guarantees implicit or otherwise are implied, your mileage may vary. =1 19 =1 20 ; Philips/Signetics 87C752 Processor Descriptor File =1 21 $NOLIST =1 185 $INCLUDE(common.inc) =1 187 ;This code is listed here for entertainment value only, it should =1 188 ;not be used for anything important. Do not use this for a saleable product. =1 189 ;Feel free to pass this on to others in it's entirety. along with this message. =1 190 ;No Guarantees implicit or otherwise are implied, your mileage may vary. =1 193 =1 194 ; Memory Map =1 195 ; Location Code Data =1 196 ; 0000h iRAM Internal Bank 0 =1 197 ; 0000h iRAM R0 [Ihead] =1 198 ; 0001h iRAM R1 [Itail] =1 199 ; 0002h iRAM R2 [last temperature reading] =1 200 ; 0003h iRAM R3 [ROW] =1 201 ; 0004h iRAM R4 [COL] =1 202 ; 0005h iRAM R5 unused? =1 203 ; 0006h iRAM R6 [temporary] =1 204 ; 0007h iRAM R7 [temporary] =1 205 =1 206 ; 0008h iRAM Internal Bank 1 =1 207 ; 0008h iRAM R0 [ohead] =1 208 ; 0009h iRAM R1 [otail] =1 209 ; 000ah iRAM R2 [MYSW] =1 210 ; 000a.0 iRAM [MYSW.0] RAW =1 211 ; 000a.1 iRAM [MYSW.1] COLOR =1 212 ; 000a.2 iRAM [MYSW.2] BROADCAST =1 213 ; 000bh iRAM R3 [OLDCHAR] =1 214 ; 000ch iRAM R4 [OLDTEMP] =1 215 ; 000dh iRAM R5 IBUF[0] =1 216 ; 000eh iRAM R6 IBUF[1] =1 217 ; 000fh iRAM R7 IBUF[2] =1 218 =1 219 ; 0010h iRAM Internal Bank 2 =1 220 ; 0010h iRAM R0 IBUF[3] PUTCHAR Sat Jan 08 19:40:42 2005 PAGE 2 LOC OBJ LINE SOURCE =1 221 ; 0011h iRAM R1 IBUF[4] =1 222 ; 0012h iRAM R2 IBUF[5] =1 223 ; 0013h iRAM R3 IBUF[6] =1 224 ; 0014h iRAM R4 IBUF[7] =1 225 ; 0015h iRAM R5 IBUF[8] =1 226 ; 0016h iRAM R6 IBUF[9] =1 227 ; 0017h iRAM R7 OBUF[0] =1 228 =1 229 ; 0018h iRAM Internal Bank 3 =1 230 ; 0018h iRAM R0 OBUF[1] =1 231 ; 0019h iRAM R1 OBUF[2] =1 232 ; 001ah iRAM R2 OBUF[3] =1 233 ; 001bh iRAM R3 OBUF[4] =1 234 ; 001ch iRAM R4 OBUF[5] =1 235 ; 001dh iRAM R5 OBUF[6] =1 236 ; 001eh iRAM R6 OBUF[7] =1 237 ; 001fh iRAM R7 OBUF[8] =1 238 =1 239 ; 0020h iRAM Internal (Stack start) =1 240 ; 0080h RAM Internal P0 =1 241 ; 0081h RAM Internal SP =1 242 ; 0082h RAM Internal DPL =1 243 ; 0083h RAM Internal DPH =1 244 ; 0084h RAM Internal nothing =1 245 ; 0087h RAM Internal nothing =1 246 ; 0088h RAM Internal TCON =1 247 ; 0089h RAM Internal TMOD =1 248 ; 008ah RAM Internal TL0 =1 249 ; 008bh RAM Internal TL1 =1 250 ; 008ch RAM Internal TH0 =1 251 ; 008dh RAM Internal TH1 =1 252 ; 008eh RAM Internal nothing =1 253 ; 008fh RAM Internal nothing =1 254 ; 0090h RAM Internal P1 =1 255 ; 0091h RAM Internal nothing =1 256 ; 0097h RAM Internal nothing =1 257 ; 0098h RAM Internal SCON =1 258 ; 0099h RAM Internal SBUF =1 259 ; 009ah RAM Internal nothing =1 260 ; 009fh RAM Internal nothing =1 261 ; 00a0h RAM Internal P2 =1 262 ; 00a1h RAM Internal nothing =1 263 ; 00a7h RAM Internal nothing =1 264 ; 00a8h RAM Internal IEC =1 265 ; 00a9h RAM Internal nothing =1 266 ; 00afh RAM Internal nothing =1 267 ; 00b0h RAM Internal P3 =1 268 ; 00b1h RAM Internal nothing =1 269 ; 00b7h RAM Internal nothing =1 270 ; 00b8h RAM Internal IPC =1 271 ; 00b9h RAM Internal nothing =1 272 ; 00cfh RAM Internal nothing =1 273 ; 00d0h RAM Internal PSW =1 274 ; 00d1h RAM Internal nothing =1 275 ; 00dfh RAM Internal nothing =1 276 ; 00e0h RAM Internal ACC =1 277 ; 00e1h RAM Internal nothing =1 278 ; 00efh RAM Internal nothing =1 279 ; 00f0h RAM Internal B =1 280 ; 00f1h RAM Internal nothing =1 281 ; 00ffh RAM Internal nothing =1 282 =1 283 PUTCHAR Sat Jan 08 19:40:42 2005 PAGE 3 LOC OBJ LINE SOURCE =1 284 ;COLS EQU 40 =1 285 ;ROWS EQU 4 0010 =1 286 COLS EQU 16 0001 =1 287 ROWS EQU 1 =1 288 0003 =1 289 ROW EQU 03h 0004 =1 290 COL EQU 04h =1 291 000A =1 292 MYSW EQU 0Ah 000B =1 293 OLDCHAR EQU 0Bh 000C =1 294 OLDTEMP EQU 0Ch =1 295 0000 =1 296 RAW EQU 0 0001 =1 297 COLOR EQU 1 0002 =1 298 BROADCAST EQU 2 =1 299 0095 =1 300 SRD EQU P1.5 0097 =1 301 SWR EQU P1.7 0094 =1 302 CTS EQU P1.4 ; Goes low when OK to send or receive. =1 303 =1 304 ; The following BCASTs better match the alarms versions. 00FE =1 305 BCAST_ON EQU 254 ; Broadcast on char. 00FD =1 306 BCAST_OFF EQU 253 ; Broadcast off char. =1 307 =1 308 ; R5 used for getchar routine. =1 309 ; R6 =1 310 ; R7 are temporaries. 0005 =1 311 R05 EQU 05h 0006 =1 312 R06 EQU 06h 0007 =1 313 R07 EQU 07h =1 314 000D =1 315 IBUFSTART EQU 0Dh 0017 =1 316 IBUFEND EQU 17h ; Up to but not including. =1 317 0017 =1 318 OBUFSTART EQU 17h 0020 =1 319 OBUFEND EQU 20h ; Up to but not including. =1 320 =1 321 ; At 9600 baud, 104.166667 usec/bit. at 5.24288MHz 1 cycle = 2.28882usec. =1 322 ; number of cycles per bit is 104.166667 / 2.28882 in this case or, =1 323 ; 46 (45.51) cycles per bit. 002E =1 324 CPB EQU 46 ; Cycles per bit. =1 325 326 sleep MACRO W 327 MOV DPTR,#NOT((W-5)/6) ; 2 cycles 328 ACALL LONGWAIT ; 2 cycles 329 ENDM =1 330 331 ; Put Character routine 332 333 CLIBC SEGMENT CODE 334 RSEG CLIBC 335 336 PUBLIC PUTCHAR 337 PUBLIC IPUTCHAR 338 0000 339 PUTCHAR: 340 ; char is put in *R1 0000 C2AF 341 CLR EA ; Turn off interrupts, a critical section. 0002 D2D3 342 SETB RS0 ; Use register bank 1. 0004 F7 343 MOV @R1,A ; put character into output buffer. 0005 09 344 INC R1 ; move output buffer head, wrap around if end. 0006 B92002 345 CJNE R1,#OBUFEND,RETPUTC 0009 7917 346 MOV R1,#OBUFSTART PUTCHAR Sat Jan 08 19:40:42 2005 PAGE 4 LOC OBJ LINE SOURCE 000B 347 RETPUTC: 000B C2D3 348 CLR RS0 ; get back to register bank 0 000D D2AF 349 SETB EA ; reenable interrupts and leave. 000F 22 350 RET 351 352 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 353 ; IPUTCHAR 354 ; Takes character in ACC and puts it out SWR 9600,N,8,1 355 ; uses R6 and R7 but these are free for other usage since this code 356 ; doesn't get interrupted. 357 ; 358 ; CPB cycles per bit. 359 ; 360 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 361 0010 362 IPUTCHAR: 0010 C2AF 363 CLR EA ; Disable all interrupts until character is out 0012 D2D3 364 SETB RS0 ; Register bank 1 contains output buffer data 0014 E8 365 MOV A,R0 0015 C3 366 CLR C 0016 99 367 SUBB A,R1 0017 6023 368 JZ BAILOUT 0019 E6 369 MOV A,@R0 370 001A 371 WRITEBUFOK: 001A C2D3 372 CLR RS0 ; Register bank 0 needs to be reset. 001C F4 373 CPL A ; RS 232 is expecting inverted output. 374 ; 1 cycle 001D 7E09 375 MOV R6,#9 ; 9 Bits out(1start plust 8 bits), plus stop 376 ; bit.. 377 ; 1 cycle 378 ;write first (one) bit. 001F D3 379 SETB C ; 1 cycle 380 381 ; loop=( base cycles - 7 for bit setup overhead ) / 2 382 ; R7 will contain the time necessary to match 9600 baud. 0020 383 PNEXTBIT: 0020 9297 384 MOV SWR,C ; 2 cycles 0022 7F13 385 MOV R7,#(CPB-7)/2 ; 1 cycle 386 387 ;sleep 0024 DFFE 388 DJNZ R7,$ ; 2 cycles 389 +1 IF ((CPB-7) MOD 2) > 0 0026 00 390 +1 NOP 391 +1 ENDIF 0027 C3 392 CLR C ; 1 cycles 0028 13 393 RRC A ; 1 cycles 0029 DEF5 394 DJNZ R6,PNEXTBIT ; 2 cycles 395 396 ;write two stop (zero) bits. 002B C297 397 CLR SWR ; 1 cycle 398 399 400 ; loop=(base cycles - 1 ) * 2 / 2 002D 7F2D 401 MOV R7,#(CPB-1) ; 1 cycle 402 403 ; sleep 002F DFFE 404 DJNZ R7,$ ; 2 cycles 405 0031 209408 406 JB CTS,BAILOUT ; Character didn't make it, try again later. 407 ; What happened was the master moved on 408 ; after telling us it was ok to transmit. 0034 D2D3 409 SETB RS0 ; Register bank 1 contains output buffer data PUTCHAR Sat Jan 08 19:40:42 2005 PAGE 5 LOC OBJ LINE SOURCE 0036 08 410 INC R0 ; Update output buffer, since we actually 411 ; got the character out. 0037 B82002 412 CJNE R0,#OBUFEND,BAILOUT 003A 7817 413 MOV R0,#OBUFSTART ; and wrap if necessary. 003C 414 BAILOUT: 003C C2D3 415 CLR RS0 ; get back to register bank 0 003E D2AF 416 SETB EA ; Reenable all interrupts now. 0040 22 417 RET ; and leave. 418 $EJECT PUTCHAR Sat Jan 08 19:40:42 2005 PAGE 6 LOC OBJ LINE SOURCE 419 END 420 PUTCHAR Sat Jan 08 19:40:42 2005 PAGE 7 SYMBOL TABLE LISTING ------ ----- ------- N A M E T Y P E V A L U E A T T R I B U T E S AADR0...... NUMB 0001H A AADR1...... NUMB 0002H A AADR2...... NUMB 0004H A AC......... B ADDR 00D0H.6 A ACC........ D ADDR 00E0H A ADAT....... D ADDR 0084H A ADCI....... NUMB 0010H A ADCON...... D ADDR 00A0H A ADCS....... NUMB 0008H A ARL........ B ADDR 0098H.4 A ATN........ B ADDR 0098H.6 A B.......... D ADDR 00F0H A BAILOUT.... C ADDR 003CH R SEG = CLIBC BCAST_OFF.. NUMB 00FDH A BCAST_ON... NUMB 00FEH A BROADCAST.. NUMB 0002H A CARL....... B ADDR 0098H.4 A CDR........ B ADDR 0098H.5 A CLIBC...... C SEG 0041H R REL = UNIT CLRTI...... B ADDR 00D8H.5 A COL........ NUMB 0004H A COLOR...... NUMB 0001H A COLS....... NUMB 0010H A CPB........ NUMB 002EH A CSTP....... B ADDR 0098H.2 A CSTR....... B ADDR 0098H.3 A CT0........ B ADDR 00D8H.0 A CT1........ B ADDR 00D8H.1 A CTS........ B ADDR 0090H.4 A CXA........ B ADDR 0098H.7 A CY......... B ADDR 00D0H.7 A DPH........ D ADDR 0083H A DPL........ D ADDR 0082H A DRDY....... B ADDR 0098H.5 A EA......... B ADDR 00A8H.7 A EI2........ B ADDR 00A8H.4 A EN......... NUMB 0040H A EN2........ NUMB 0080H A ENADC...... NUMB 0020H A EPWM....... B ADDR 00A8H.3 A ET0........ B ADDR 00A8H.1 A EX0........ B ADDR 00A8H.0 A EX1........ B ADDR 00A8H.2 A F0......... B ADDR 00D0H.5 A GATE....... B ADDR 0088H.7 A I2CFG...... D ADDR 00D8H A I2CON...... D ADDR 0098H A I2DAT...... D ADDR 0099H A I2STA...... D ADDR 00F8H A IBUFEND.... NUMB 0017H A IBUFSTART.. NUMB 000DH A IDLE....... B ADDR 0098H.6 A IDLES...... B ADDR 00F8H.6 A IE......... D ADDR 00A8H A IE0........ B ADDR 0088H.3 A IE1........ B ADDR 0088H.1 A INT0....... B ADDR 0090H.5 A INT1....... B ADDR 0090H.6 A IPUTCHAR... C ADDR 0010H R PUB SEG = CLIBC IT0........ B ADDR 0088H.2 A IT1........ B ADDR 0088H.0 A KP_C1...... B ADDR 00B0H.5 A KP_C2...... B ADDR 00B0H.4 A KP_C3...... B ADDR 00B0H.0 A KP_C4...... B ADDR 00B0H.1 A KP_C5...... B ADDR 00B0H.2 A KP_C6...... B ADDR 00B0H.3 A KP_R1...... B ADDR 0080H.3 A KP_R2...... B ADDR 0080H.2 A KP_R3...... B ADDR 0090H.0 A KP_R4...... B ADDR 0090H.1 A LCD_D4..... B ADDR 00B0H.0 A LCD_D5..... B ADDR 00B0H.1 A LCD_D6..... B ADDR 00B0H.2 A LCD_D7..... B ADDR 00B0H.3 A LCD_EN..... B ADDR 00B0H.6 A LCD_EN2.... B ADDR 00B0H.7 A LCD_RS..... B ADDR 00B0H.5 A LCD_RW..... B ADDR 00B0H.4 A MAKSTP..... B ADDR 00F8H.2 A MAKSTR..... B ADDR 00F8H.3 A MASTER..... B ADDR 0098H.1 A MASTRQ..... B ADDR 00D8H.6 A MYSW....... NUMB 000AH A OBUFEND.... NUMB 0020H A OBUFSTART.. NUMB 0017H A OLDCHAR.... NUMB 000BH A OLDTEMP.... NUMB 000CH A OV......... B ADDR 00D0H.2 A P.......... B ADDR 00D0H.0 A P0......... D ADDR 0080H A P0_0....... B ADDR 0080H.0 A P0_1....... B ADDR 0080H.1 A P0_2....... B ADDR 0080H.2 A P1......... D ADDR 0090H A P1_0....... B ADDR 0090H.0 A P1_1....... B ADDR 0090H.1 A P1_2....... B ADDR 0090H.2 A P1_3....... B ADDR 0090H.3 A P1_4....... B ADDR 0090H.4 A P1_5....... B ADDR 0090H.5 A P1_6....... B ADDR 0090H.6 A P1_7....... B ADDR 0090H.7 A P3......... D ADDR 00B0H A P3_0....... B ADDR 00B0H.0 A P3_1....... B ADDR 00B0H.1 A P3_2....... B ADDR 00B0H.2 A P3_3....... B ADDR 00B0H.3 A P3_4....... B ADDR 00B0H.4 A P3_5....... B ADDR 00B0H.5 A P3_6....... B ADDR 00B0H.6 A P3_7....... B ADDR 00B0H.7 A PCON....... D ADDR 0087H A PNEXTBIT... C ADDR 0020H R SEG = CLIBC PSW........ D ADDR 00D0H A PUTCHAR.... C ADDR 0000H R PUB SEG = CLIBC PWCM....... D ADDR 008EH A PWENA...... D ADDR 00FEH A PWMP....... D ADDR 008FH A R05........ NUMB 0005H A R06........ NUMB 0006H A R07........ NUMB 0007H A RAW........ NUMB 0000H A RDAT....... B ADDR 0098H.7 A RETPUTC.... C ADDR 000BH R SEG = CLIBC ROW........ NUMB 0003H A ROWS....... NUMB 0001H A RS0........ B ADDR 00D0H.3 A RS1........ B ADDR 00D0H.4 A RTH........ D ADDR 008DH A RTL........ D ADDR 008BH A SCL........ B ADDR 0080H.0 A SDA........ B ADDR 0080H.1 A SLAVEN..... B ADDR 00D8H.7 A SP......... D ADDR 0081H A SRD........ B ADDR 0090H.5 A STP........ B ADDR 0098H.2 A STR........ B ADDR 0098H.3 A SWR........ B ADDR 0090H.7 A T0......... B ADDR 0090H.7 A TCON....... D ADDR 0088H A TF......... B ADDR 0088H.5 A TH......... D ADDR 008CH A TIRUN...... B ADDR 00D8H.4 A TL......... D ADDR 008AH A TR......... B ADDR 0088H.4 A WRITEBUFOK. C ADDR 001AH R SEG = CLIBC XACTV...... B ADDR 00F8H.4 A XDATAS..... B ADDR 00F8H.5 A XSTP....... B ADDR 0098H.0 A XSTPS...... B ADDR 00F8H.0 A XSTR....... B ADDR 0098H.1 A XSTRS...... B ADDR 00F8H.1 A REGISTER BANK(S) USED: 0 ASSEMBLY COMPLETE, NO ERROR FOUND